As used herein, the term "semiconductor device" refers to a silicon chip or die containing circuitry, and the term "semiconductor device assembly" refers to the semiconductor chip and associated packaging containing the chip, including leads such as for connecting to a socket or a circuit board, and internal connections, such as bond wires, of the chip to the leads.
Commonly-owned U.S. Pat. No. 4,800,419, entitled SUPPORT ASSEMBLY FOR INTEGRATED CIRCUITS, discloses a composite support assembly for an integrated circuit chip. The support assembly includes a rigid lead frame that is attached to a relatively thin, flexible, tape-like structure. The tape-like structure includes a metallic layer that is etched with inner and outer lead "fingers" allowing for a short pitch, high density arrangement of the lead fingers, thereby enabling bond wires that connect a semiconductor chip to the support assembly to be relatively short. The metallic layer is supported by a segmented plastic film layer, preferably formed of KAPTON (trademark of DuPont Corp.).
Commonly-owned U.S. Pat. No. 4,771,330, entitled WIRE BONDS AND ELECTRICAL CONTACTS OF AN INTEGRATED CIRCUIT DEVICE, discloses an integrated circuit device package including a rigid frame and flexible tape assembly having wire leads between the die attach pad, conductive lead fingers and the integrated circuit (IC) chip. A dam structure prevents resin flow to ensure proper wire bonding.
Commonly-owned, copending U.S. patent application Ser. No. 115,228, entitled METHOD AND MEANS OF FABRICATING A SEMICONDUCTOR DEVICE PACKAGE and filed on Oct. 30, 1987, discloses a semiconductor device assembly having a patterned conductive layer, including a die attach pad and a plurality of leads, and a patterned insulating layer. A semiconductor die is seated on the die attach pad and is connected, such as by bond wires, to the leads. A silicone gel, such as Dow Corning Q1-4939, having a 1 to 10 mixing ratio of curing agent to base, is applied over the bond wires. A body frame, preferably made of a polymer material such as RYTON (trademark of Phillips Chemical Co.) is positioned around the die, and an encapsulant material, such as HYSOL CNB 405-12 (trademark of Hysol) is distributed within the RYTON frame over the semiconductor die and die connections.
Commonly-owned, copending U.S. patent application Ser. No. 380,174, entitled STRIP CARRIER FOR INTEGRATED CIRCUITS and filed on Jul. 14, 1989, discloses a semiconductor device assembly having a patterned conductive layer and a patterned insulating layer, and mounted to a strip carrier providing mechanical rigidity to the semiconductor device assembly during assembly thereof. After assembly, the packaged semiconductor device assembly is excised from the strip carrier.
The aforementioned, commonly-owned patents and applications relate to semiconductor device assemblies having a high lead count. Generally, the inner leads of these devices extend to the periphery of the semiconductor die, and the die is mounted to a die attach pad directly under the die. In the case of wire bonding the die to the inner leads, the inner leads extend only nearly to the four peripheral edges of the typically square die. In other words, the inner leads are directed to a central point, directly under the die, but stop short thereof--the innermost ends of the inner leads defining a square "cavity" locating and containing the die and, where there is one, a die attach pad. In the case of TAB (Tape Automated Bonding) the die to the inner leads, the inner leads extend uniformly just inside the peripheral edges of the die. In the main hereinafter, wire bonding is discussed.
The inner leads "fan out" from their innermost ends, adjacent the die attach pad. Typical dimensions for the inner leads are 21/2 mils (thousandths of an inch) wide, with an spacing of 4 mils between adjacent leads at their innermost ends.
In the prior art, multiple cavity sizes of leadframes were required to accommodate a broad range of die sizes. Further, die attach pads were commonly used. However, the technology is evolving towards the use of tape-based substrates, versus lead frames, and towards the use of epoxy-based die attach techniques not requiring a die attach pad.
U.S. Pat. No. 4,195,193 discloses a lead frame and chip carrier housing. Therein is disclosed a lead frame having a central support portion and leads extending from the support portion in all directions. FIG. 2 shows the basic lead frame, and FIGS. 3-5 show how chips of varying sizes and requiring varying numbers of leads can be accommodated by the lead frame. Generally, only some of the leads extend all the way to the support portion, and the remaining leads terminate increasingly further away from the support portion in a symmetrical radiating pattern. According to the size of the die, and the number of connections to be made, the central support portion (including the ends of the longest leads) is removed, the chip is placed in the resulting square opening (which is at least as large as the die), and the die is connected to those leads extending to the opening. Hence, the larger the opening in the center of the lead frame is made, the greater number of leads become available for connection to the die.
U.S. Pat. No. 4,190,855 discloses installation of a semiconductor chip on a glass substrate. A flipchip LSI (3) is mounted on a glass substrate (1) having a wiring pattern (2). The wiring pattern extends, evidently, to a fixed distance just inside the perimeter of the flipchip so that solder (4) connections can be made between attachment points about the perimeter of the flipchip (3) and the inner ends of the conductors (2).
U.S. Pat. No. 4,258,381 discloses a lead frame for a semiconductor device suitable for mass production. Therein is disclosed a lead frame assembly having an "island" (5) at its center portion for mounting a semiconductor chip, and leads (7) positioned around the island for completing to electrical connection with external circuits. The chip is wire bonded to the leads in a normal manner.
U.S. Pat. No. 4,772,936 discloses a pre-testable double-sided TAB design. Therein is disclosed a flip-chip device (150) having solder bumps (122') mounted to a tape (110) having leads (120) crossing gaps (130) in the tape to positions underneath the device (150). The flip-chip device (150) is mounted without a die attach pad.
Attention is also directed to U.S. Pat. No. 3,984,860, which discloses multi-function LSI wafers, and to U.S. Pat. No. 4,080,512, which discloses a substrate for integrated circuit.